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[ÄÄÆÄÀÏ·¯] LEX·Î ±¸ÇöÇÑ Lexical Analyzer

[ÄÄÆÄÀÏ·¯] LEX·Î ±¸ÇöÇÑ Lexical Analyzer

1. ¼­·Ð 2. º»·Ð 1) ÀýÂ÷¿¡ µû¸¥ »ý¼º ÆÄÀÏ 2) Lex ±â¼ú¾ç½Ä 3) Lex ¿î¿µ ¹æ½Ä 3. °á·Ð FileSize : 37K / 1. ¼­·Ð 2. º»·Ð 1) ÀýÂ÷¿¡ µû¸¥ »ý¼º ÆÄÀÏ 2) Lex ±â¼ú¾ç½Ä 3) Lex ¿î¿µ ¹æ½Ä 3. °á·Ð / 1. ¼­·Ð lexical analyzer¸¦ ±¸ÇöÇÏ´Â Lex¸¦ ÀÌ¿ëÇÏ¿© ¿ì¸®°¡ ¿¹Àü¿¡ finite-automata ÀÛ¼ºÇß´ø lexical analyzer¸¦ ±¸ÇöÇØ º¸µµ·Ï ÇÏÀÚ.
·¹Æ÷Æ® > °øÇбâ¼ú   4page   1,100 ¿ø
[ÀÚ¿¬°úÇÐ] Protocol Analyzer ¸¦ ÀÌ¿ëÇÑ ÆÐŶ ºÐ¼®

[ÀÚ¿¬°úÇÐ] Protocol Analyzer ¸¦ ÀÌ¿ëÇÑ ÆÐŶ ºÐ¼®

[ÀÚ¿¬°úÇÐ] Protocol Analyzer ¸¦ ÀÌ¿ëÇÑ ÆÐŶ ºÐ¼® - ¹Ì¸®º¸±â¸¦ Âü°í ¹Ù¶ø´Ï´Ù. / * Protocol Analyzer ¸¦ ÀÌ¿ëÇÑ ÆÐŶ ºÐ¼® [Explorer ÀÌ¿ëÇÑ http://www.naver.com Á¢¼Ó] ¢º Broadcast À» ÅëÇÑ Naver.com °Ë»ö (1) Ethernet v2.0 MAC Header Destination MAC Address : FF FF FF FF FF FF FFBroadcastSource MAC Address : 00 50 FC EC A7 39Type : 08 00IP (2) IPv4 Header Ver¡¦
·¹Æ÷Æ® > ÀÚ¿¬°úÇÐ   24page   3,000 ¿ø
¹«·á´Ù¿î·Îµå::Á¦¾î°èÃøÀÚ·á::Spectrum Analyzer::PPT¹ßÇ¥ÀÚ·á::·¹Æ÷Æ®´Ù¿î

¹«·á´Ù¿î·Îµå::Á¦¾î°èÃøÀÚ·á::Spectrum Analyzer::PPT¹ßÇ¥ÀÚ·á::·¹Æ÷Æ®´Ù¿î

[Á¦¾î°èÃøÀÚ·á]Spectrum Analyzer PPT¹ßÇ¥ÀÚ·áÀÔ´Ï´Ù. / Spectrum Analyzer & FFT Analyzer À̶õ Spectrum Analyzer ¿ø¸® - ÀÔ·Â´Ü : ÃÖÀû ÀÔ·Â ·¹º§ , ÃÖ´ë Çã¿ë ÀÔ·Â ·¹º§ - Dynamic Range Oscillosco¡¦
·¹Æ÷Æ® > °øÇбâ¼ú   36page   3,000 ¿ø
[ÀÚ¿¬°úÇÐ] [Çö´ë¹°¸®ÇнÇÇè]  DRIVEN HARMONIC MOTION ANALYZER - µå¸®ºì Çϸð´Ï ¿îµ¿ Ư¼º ÀÌÇØ

[ÀÚ¿¬°úÇÐ] [Çö´ë¹°¸®ÇнÇÇè] DRIVEN HARMONIC MOTION ANALYZER - µå¸®ºì Çϸð´Ï ¿îµ¿ Ư¼º ÀÌÇØ

[ÀÚ¿¬°úÇÐ] [Çö´ë¹°¸®ÇнÇÇè] DRIVEN HARMONIC MOTION ANALYZER - µå¸®ºì Çϸð´Ï ¿îµ¿ Ư¼º ÀÌÇØ / Çö´ë¹°¸®ÇнÇÇè -DRIVEN HARMONIC MOTION ANALYZER 1. ³¯Â¥ : 2. Á¶¿ø : 3. Á¦¸ñ : DRIVEN HARMONIC MOTION ANALYZER 4. ¸ñÀû : ½ÇÇèÀ» ÅëÇØ HARMONIC MOTIONÀÇ Æ¯¼ºÀ» ÀÌÇØÇÑ´Ù. 5. ÀÌ·Ð 1) ÈÅÀǹýÄ¢ : F ¡ë -kx 2) Á¶È­¿îµ¿ : ÀÏÁ¤ÇÑ ½Ã°£°£°ÝÀ» µÎ°í µÇÇ®ÀÌ ÇÏ´Â ¿îµ¿À» Á¶È­¿î¡¦
½ÇÇè°úÁ¦ > ¹°¸®È­ÇÐ   11page   2,000 ¿ø
Àü±âÈ­ÇÐ ºÐ¼®±â (Electrochemical analyzer)

Àü±âÈ­ÇÐ ºÐ¼®±â (Electrochemical analyzer)

Àü±âÈ­ÇÐ ºÐ¼®±â (Electrochemical analyzer) ¼­ºê³ëÆ®ÀÔ´Ï´Ù. °ü·Ã ¸®Æ÷Æ®³ª ½ÃÇèÀ» ÁغñÇϽô ºÐµé²² ¸¹Àº È°¿ëÀÌ µÇ½Ã±æ ºô¸ç, ÇູÇÑ ½Ã°£ µÇ¼¼¿ä. ecs322 / 1. Àü±âÈ­ÇÐ ÃøÁ¤¹ýÀÇ ºÐ·ù 2.1 Àü±ØÇ¥¸é¿¡¼­ ÀüÀÚ¸¦ ÁÖ°í ¹Þ´Â °úÁ¤ ¹× Àü¾Ð-Àü·ù°ü°è 3. Á÷·ù Æú¶ó·Î±×·¡ÇÇ 4. »õ·Î¿î Æú¶ó·Î±×·¡ÇÇ 5. Àü¾Ð-Àü·ù¹ý 6. ÀüÇع«°Ô ºÐ¼®¹ý ¹× Àü±â·®¹ý 6.1 ÀÏÁ¤ÀüÀ§ ÀüÇØ ¹× ÀÏÁ¤Àü·ù¡¦
·¹Æ÷Æ® > ±âŸ   30page   3,000 ¿ø
°£´ÜÇÑ C¾ð¾î lexical analyzer

°£´ÜÇÑ C¾ð¾î lexical analyzer

°£´ÜÇÑ C¾ð¾î lexical analyzer¿¡ ´ëÇÑ ±ÛÀÔ´Ï´Ù. °£´ÜÇÑC¾ð¾îlexicalanalyzer / ---------<end of test.c>----------------------------------------------------- ---------<result-->---------------------------------------------------------- [genius@hongki_note lex]$ ./lexer4c text.c Reserved Word Count: 4 ID Count: 16 NUM Count: 1 Line Count: 15 Word Count: ¡¦
·¹Æ÷Æ® > °øÇбâ¼ú   6page   1,000 ¿ø
[°øÇÐ] ³í¸®°ÔÀÌÆ® - VHDL ¼³°è ¾ð¾î ½Ç½À

[°øÇÐ] ³í¸®°ÔÀÌÆ® - VHDL ¼³°è ¾ð¾î ½Ç½À

[°øÇÐ] ³í¸®°ÔÀÌÆ® - VHDL ¼³°è ¾ð¾î ½Ç½À / ¡ß AND GATE(2 input) 1. ¼Ò½º library ieee; use ieee.std_logic_1164.all; entity andgate is port( sw1 : in std_logic; sw2 : in std_logic; led : out std_logic); end andgate; architecture sample of andgate is begin led `¡ë sw1 and sw2; end sample; 2. ½Ã¹Ä·¹ÀÌ¼Ç 1) Flow Summary 2) Waveform 3) time analyz¡¦
·¹Æ÷Æ® > °øÇбâ¼ú   26page   3,000 ¿ø
[ÀÚ¿¬°úÇÐ] ½ÇÇ躸°í¼­ - ±¤Åº¼º ½ÇÇè

[ÀÚ¿¬°úÇÐ] ½ÇÇ躸°í¼­ - ±¤Åº¼º ½ÇÇè

[ÀÚ¿¬°úÇÐ] ½ÇÇ躸°í¼­ - ±¤Åº¼º ½ÇÇè / ±¤Åº¼º ½ÇÇè 1.½ÇÇè ¸ñÀû ±¤Åº¼º ½ÇÇèÀåÄ¡(polariscope)¸¦ »ç¿ëÇÏ¿© ¿Ü·ÂÀ» ¹Þ´Â ¹°Ã¼¿¡ »ý±â´Â ÀÀ·ÂºÐÆ÷»óŸ¦ °üÂûÇÏ°í ÃøÁ¤ÇÑ´Ù. 2. ÀÌ·Ð ¹× ¿ø¸® (1) Æí±¤ ÀϹÝÀûÀ¸·Î ºûÀº ¶óµð¿ÀÆÄ(radio waves)¿Í ¸¶Âù°¡Áö·Î ÀüÀÚ±âÀû Áøµ¿À» ÇÑ´Ù. ¿¹¸¦ µé¾î ¹é¿­µîÀº »ç¹æÀ¸·Î ÆÛÁö¸ç °¢±â ´Ù¸¥ ÁÖÆļö(¶Ç´Â ÆÄÀå)·Î Áøµ¿ÇÏ´Â ¿ÏÀü ½ºÆåÆ®·³ÀÇ ºûÀ» ¡¦
½ÇÇè°úÁ¦ > ÀÚ¿¬°úÇÐ   8page   1,800 ¿ø
½ºÆåÆ®·³ ¾Æ³¯¶óÀÌÀú

½ºÆåÆ®·³ ¾Æ³¯¶óÀÌÀú

½ºÆåÆ®·³ ¾Æ³¯¶óÀÌÀúÀÇ Àü¹ÝÀûÀÎ ³»¿ëÀ» Á¶»ç Á¤¸®ÇÑ ÀÚ·áÀÔ´Ï´Ù. ÇÊ¿äÇϽŠºÐ¿¡°Ô ¿©·¯¸ð·Î µµ¿òÀÌ µÇ½Ã¸®¶ó »ý°¢ÇÕ´Ï´Ù. ¸ðµÎ ÁÁÀº °á°ú ÀÖÀ¸½Ã±æ ¹Ù¶ø´Ï´Ù. ½ºÆåÆ®·³¾Æ³¯¶óÀÌÀú / • Àü±âÀûÀÎ ½ÅÈ£ÀÇ Ç¥Çö ¹æ¹ý • ÁÖÆļö ¿µ¿ª°ú ½Ã°£ ¿µ¿ª • ÁøÆø ¿ä¼Òµé(Amplitude Factors) • ½ºÆåÆ®·³ ¾Æ³¯¶óÀÌÀú(pectrum Analyzer)¶õ • ½ºÆåÆ®·³ ¾Æ³¯¶óÀÌÀúÀÇ ¿ëµµ¡¦
·¹Æ÷Æ® > °øÇбâ¼ú   17page   2,000 ¿ø
[°øÇÐ] VHDL ¼³°è ¾ð¾î ½Ç½À(¹®¹ýÀû¿ë)

[°øÇÐ] VHDL ¼³°è ¾ð¾î ½Ç½À(¹®¹ýÀû¿ë)

[°øÇÐ] VHDL ¼³°è ¾ð¾î ½Ç½À(¹®¹ýÀû¿ë) / ¡ß logic1 1.¼Ò½º library ieee; use ieee.std_logic_1164.all; entity logic1 is port(a,b,c :in bit; y :out bit); end logic1; architecture sample of logic1 is signal w, x : bit; begin no1: process(a,b) begin if (a¡ë`1`) or (b¡ë`1`) then w `¡ë `1`; else w `¡ë`0`; end if; end process; no2:¡¦
·¹Æ÷Æ® > °øÇбâ¼ú   26page   3,000 ¿ø




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