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°£´ÜÇÑ C¾ð¾î lexical analyzer¿¡ ´ëÇÑ ±ÛÀÔ´Ï´Ù. °£´ÜÇÑC¾ð¾îlexicalanalyzer / ---------<end of test.c>----------------------------------------------------- ---------<result-->---------------------------------------------------------- [genius@hongki_note lex]$ ./lexer4c text.c Reserved Word Count: 4 ID Count: 16 NUM Count: 1 Line Count: 15 Word Count: ¡¦
[°øÇÐ] ³í¸®°ÔÀÌÆ® - VHDL ¼³°è ¾ð¾î ½Ç½À / ¡ß AND GATE(2 input) 1. ¼Ò½º library ieee; use ieee.std_logic_1164.all; entity andgate is port( sw1 : in std_logic; sw2 : in std_logic; led : out std_logic); end andgate; architecture sample of andgate is begin led `¡ë sw1 and sw2; end sample; 2. ½Ã¹Ä·¹ÀÌ¼Ç 1) Flow Summary 2) Waveform 3) time analyz¡¦
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[°øÇÐ] VHDL ¼³°è ¾ð¾î ½Ç½À(¹®¹ýÀû¿ë) / ¡ß logic1 1.¼Ò½º library ieee; use ieee.std_logic_1164.all; entity logic1 is port(a,b,c :in bit; y :out bit); end logic1; architecture sample of logic1 is signal w, x : bit; begin no1: process(a,b) begin if (a¡ë`1`) or (b¡ë`1`) then w `¡ë `1`; else w `¡ë`0`; end if; end process; no2:¡¦