|
1.fifo_gray (rtl 寃뚯씠�듃 �젅踰� �냼�뒪)
`timescale 1ns / 10ps
module fifo_gray(clk, push, pop, data, ready, empty, full);
output ready, empty, full;
input logic clk, push, pop;
inout [31:0]data;
localparam depth=2;
reg [31:0]memory[2**depth-1:0];
reg [depth-1:0]ptr[2:1];
reg [depth-1:0]bptr[2:1];
reg [depth-1:0]rptr;
reg ready, empty, full;
reg push_done,pop_done ;
logic [depth-1:0] a;
assign a= push?bptr[1]:pop?bptr[2]:0;
wire [depth-1:0] s,gptr;
initial
begin
ready =1;
empty =1;
full =0;
pop_done=1;
ptr[2] =0;
ptr[1] =0;
bptr[2] =0;
bptr[1] =0;
end
always @(posedge clk)
begin:PUSH
if(push)
begin
ready = 0;
if(!full)
begin
memory[ptr[1]] <= data;
ptr[1] = gptr;
bptr[1]= s;
end
if(push_done &&(ptr[2]==ptr[1]))
full=1;
end
if(pop)
full=0;
end
always @(posedge clk or negedge pop)
begin:POP
if(!empty && pop)
begin
bptr[2] = s;
ptr[2]=gptr;
���(�깮�왂)
|
#20 pop=0; push=0;
#20 pop=1; push=0; release data ;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h54;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h55;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h56;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h57;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h58;
#20 pop=0; push=0;
#20 push=1; pop=0;force data=8h59;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
#20 pop=1; push=0;
#20 pop=0; push=0;
end
endmodule
인 쇄
바로가기
Fifo_Gray.zip
[Size :
191 Kbyte
]
장바구니
