DESIGN
REPORT
º¹ÀâÇÑ È¸·Î ¼³°è
- 4ºñÆ® °¡»ê±â -
°ú ¸ñ :
ÇÐ °ú :
ÇÐ ¹ø :
ÀÌ ¸§ :
Á¦ÃâÀÏÀÚ:
1. 4bit Adder ¼Ò°³
4ºñÆ® °¡»ê±â´Â 4ºñÆ®ÀÎ 2°³ÀÇ ÀԷ½ÅÈ£¸¦ ´õÇÏ´Â ¿ªÇÒÀ» ÇÑ´Ù. ¿¹¸¦ µé¾î 1xxx + 1100 = 1xxx1ÀÌ´Ù.
±âº»ÀûÀÎ 4ºñÆ® º´·Ä °¡»ê±â´Â 4°³ÀÇ Àü°¡»ê±â·Î ±¸¼ºµÈ´Ù.
µÎ °³ÀÇ ÀÔ·Â ½ÅÈ£´Â , ·Î ÁÖ¾îÁö¸ç, °¢ °¡»ê±âÀÇ Ä³¸® Ãâ·ÂÀº ´ÙÀ½ »óÀ§ °¡»ê±âÀÇ Ä³¸® ÀÔ·ÂÀÌ µÈ´Ù.
2. ¼³°è ³»¿ë
¡å ¼³°è ¹æ¹ý
4ºñÆ® °¡»ê±â´Â ºñÆ® ´ÜÀ§ÀÇ Adder 4°³¸¦ º´·Ä·Î ÇÕÃÄ ³õÀº °ÍÀ¸·Î ´ÜÀ§ Adder¸¦ ¸ÕÀú ¼³°èÇÑ ÈÄ ÄÄÆ÷³ÍÆ®¹®À» »ç¿ëÇÑ ±¸Á¶Àû Ç¥ÇöÀ¸·Î ÄÚµùÇÒ ¼ö ÀÖ´Ù.
¡å Bit AdderÀÇ ÄÚµå ³»¿ë
LIBRARY ieee; USE ieee.std_logic_1164.all; Library¿Í Package¼±¾ð
ENTITY bitadder IS
PORT (A1, B1, CIN : IN std_logic;
COUT, SUM1 : OUT std_logic); ÀÔÃâ·Â Æ÷Æ® ¼±¾ð
END bitadder;
ARCHITECTURE sample OF bitadder IS
SIGNAL S1, S2, S3 : std_logic; ½ÅÈ£ ¼±¾ð
B¡¦(»ý·«)
S3 `= CIN AND s1;
A4 A3 A2 A1 = 1100
|
COUT SUM[1] SUM[2] SUM[3] SUM[4]
11000
Ãâ·Â°ª
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` 4-ºñÆ® °¡»ê±âÀÇ Áø¸®Ç¥ `
n = 1 : =0, =0, =0 Áø¸®Ç¥ÀÇ Ã¹ ¹ø° ÁٷκÎÅÍ =0ÀÌ°í =0
n = 2 : =0, =0, =0 Áø¸®Ç¥ÀÇ Ã¹ ¹ø° ÁٷκÎÅÍ =0ÀÌ°í =0
n = 3 : =1, =1, =0 Áø¸®Ç¥ÀÇ ³× ¹ø° ÁٷκÎÅÍ =0ÀÌ°í =1
n = 4 : =1, =1, =1 Áø¸®Ç¥ÀÇ ¸¶Áö¸· ÁٷκÎÅÍ =1ÀÌ°í =1
°¡ Ãâ·Â ij¸®°¡ µÇ°í, µû¶ó¼ 1100 + 1100 = = 11000